Personal Statement
Name: Codrin Pruteanu
Personal:
Driving license: type B
E-mail: codrin.pruteanu@gmail.com
Studies:
High School (1992 - 1996):
National College;, department: Informatics - Mathematics
Certificate: PC operator
University (1996 - 2001):
(1996-2001) undergraduate student, Faculty of Automatic Control and Computer Engineering
(2001-2002) graduate student,Applications of Advanced Computing Architectures
(2002-2006) PhD. student, Research field: Applications of Artificial Intelligence in Advanced Logic Synthesis - FSM decomposition algorithms using Evolutionary Computing
Computer skills:
Programming Languages: C/C++, Tcl/Tk , Perl, Python, Pascal, Basic, Assembly, Html/Cgi/MySQL;
Operating Systems: Unix (Solaris, Linux, HP-UX), Microsoft Windows, CPM/MS-DOS;
Computer Networking: architectures with Cisco Catalyst Series and RSM Routing Module, Cisco IOS 12.x
Modeling/Simulation Environments:
GNU/egcs compiler under Unix, Microsoft Visual C++ on Microsoft Windows
Tcl/Tk and Gtk/Qt - for building cross operating systems IDE
Verilog/VHDL on ModelSim from Mentor Graphics, LeonardoSpectrum Xilinx Foundation Series, Synplify from Synplicity
LabView used as a visual development and testing language from National Instruments
Source Control Software:
Subversion / CVS and Bugzilla in order to create/maintain the repository and bug tracking
GIT / GitLab and Atlassian Jira for agile project management and software design
IBM Rational ClearCase/ClearQuest and Doors - tools for complete software and requirements management
Jenkins for Continuous Integration and software automation
PC hardware maintenance;
Experience:
Implemented Projects using: C/C++/STL, Verilog/VHDL, Tcl/Tk, Perl, Python, MySQL
Work experience with FPGA Advantage complete design flow from Mentor Graphics , design_analyzer from Synopsys
Digital IC Design using Encounter and LVS verification using Assura LVS from Cadence
Hierarchical Placement and Routing using Tempest Block and Tempest Cell from Sycon design
SIS - System for Synthesis of Sequential Circuits, VIS - Verification Interacting with Synthesis, MVSIS - Multi-valued Logic Synthesis from Berkeley University of California, CAD-Group.
Xilinx ISE Design suite for Targeted Design Platforms
CUDD - CU Decision Diagram Package, University of Colorado at Boulder
Finished Projects:
GUI tool with a powerful texteditor written in C and Tcl/Tk for Windows/Unix, with a friendly user interface
Complete IDE tool written in C++ and QT4, with advanced editing and debug facilities
Client/Server applications: ftp client , Java rmi client for reading the stock prices
Smart SoundMaker device using a PIC16F84 from Microchip
Traffic Light Controller by programming a 80x51 family microcontroller
Some little Verilog projects with Am29xx Bit-slices from AMD, i8237/8251/8255 peripherals
Verilog Synthesizable model of the Data Encryption Standard (DES) using 8 different input keys
Diploma research thesis: "The Poage-McCluskey method for testing Sequential Circuits";
Finite State Machine Generator which randomly generates completely or incompletely specified deterministic FSM's in kiss2/verilog output format.
Kiss to Verilog FSM Converter used to translate a state transition table from kiss input format to verilog output format.
A Complex FSM decomposition tool created to evolve the behaviour of a FSM by respecting optimization constraints such as Fanin/Fanout/Area.
Dissertation research thesis: Sequential Logic Synthesis - Finite State Machine Composition and Decomposition
Publications:
PRUTEANU CODRIN: Istoria sistemelor de calcul - Evolutia cunoasterii, 7 Iunie, 2011, Comitetul Roman pentru Istoria si Filosofia Stiintei si Tehnicii, Academia Romana, Bucuresti, Romania
PRUTEANU CODRIN, C.G. HABA: GenFSM, a finite state machine generation tool, Proceedings on The 9th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, ISSN 1844-5020, 22-24 May, 2008 (DAS 2008), Suceava, Romania
PRUTEANU CODRIN, CALISTRU C.N., C.G. HABA: Placement algorithms optimization based on geometric partitioning and global routing, Proceedings of the 5th International Conference on "Microelectronics and Computer Science" (ICMS), Eds., T.M. Tyginianu, I. Balmus, V. Ababii, ISBN 978-9975-45-046-1, 19-21 Sept 2007, Chisinau, Moldova
PRUTEANU CODRIN, GALEA DAN, HABA CRISTIAN-GYOZO: An Extrinsic Evolvable Hardware Approach to Logic Synthesis Optimization, Proceedings on The 8th International Conference on Development and Application Systems (DAS 2006), ISBN 973-666-194-6, 25-27 May 2006, pg. 277-280, Suceava, Romania;
PRUTEANU CODRIN, GALEA DAN, HABA CRISTIAN-GYOZO: Application of Finite State Machine General Decomoposition Method with Optimization, Proceedings on The 8th International Conference on Development and Application Systems (DAS 2006), ISBN 973-666-194-6, 25-27 May 2006, pg. 325-332, Suceava, Romania;
Cristian-Gyozo Haba, Vasile Bahrin, Codrin Pruteanu: INDIPHASO e-learning system - access to software tools for digital design computer simulation of the dynamics of virus spreading, Journal of Medical Informatics & Technologies, Vol. 9 October 2005-12-14, (ISSN 1642-6037), PP. 313-320, Poland
Cristian-Gyozo Haba, Vasile Bahrin, Codrin Pruteanu: INDIPHASO e-Learning System - Access to Software Tools for Digital Design, Proceedings of Distance Learning Workshop 2005, 19-21 October, Ustron, Poland, pp.1-8, ISBN 83-922374-0-4.
PRUTEANU CODRIN, GALEA DAN, HABA CRISTIAN-GYOZO: Global Optimization in Complex Circuits Design, Proceedings on 7th IEEE International Symposium on Signals, Circuits, Systems (ISSCS 2005), vol.2, ISBN 0-7803-9029-6, IEEE Catalog Number: 05EX1038, July 14-15, 2005, pg. 785-788, Iasi, Romania;
PRUTEANU CODRIN, PRUTEANU ANDREI, CALISTRU C.N.: Web Control on Internet Radio Streaming, Proceedings on 8th International Symposium on Automatic Control and Computer Science, ISBN 973-621-086-3, October 22 - 23, 2004, Iasi, ROMANIA
PRUTEANU CODRIN, GALEA DAN, HABA CRISTIAN-GYOZO, CALISTRU CATALIN: Global Optimization in Complex Circuits Design, accepted in Jurnal on The 4th WSEAS SIMULATION, MODELLING AND OPTIMIZATION (ICOSMO 2004), ISBN 960-8457-02-5, September 13-16, 2004, Izmir, Turkey;
CALISTRU CATALIN NICOLAE, PRUTEANU CODRIN: Modern Control Optimization Strategies for Low Cost Automation, accepted in Jurnal on The 4th WSEAS SIMULATION, MODELLING AND OPTIMIZATION (ICOSMO 2004), ISBN 960-8457-02-5, September 13-16, 2004, Izmir, Turkey;
PRUTEANU CODRIN, GALEA DAN: An Approach to Finite Automata Decomposition Using Genetic Algorithms, Proceedings on Third European Conference on Intelligent Systems and Technologies, (ECIT 2004), ISBN 973-7994-77-9, July 21-23, Iasi, Romania;
PRUTEANU CODRIN: Complex Circuit Design. Finite Automata Decomposition, Proceedings on The 7th International Conference on Development and Application Systems (DAS 2004), ISBN 973-666-106-7, 27-29 May 2004, pg. 294-298, Suceava, Romania;
Trainings and personal development:
Intel Sandy Bridge CPU and Platform (2013)
Operating Systems: Processes and Threads (2012)
Investors in People - Corporate Social Responsability and SA8000 standard (2011)
ISTQB Certified Tester - Foundation Level (2010)
CENELEC - European Electrotechnical Standardization (2010)
Development of Personal and Managerial skills (2009)
Grants:
A flexible system of realization and processing of the spinning-mill cotton fiber mixture, implemented by using dedicated software, Project supported under CNCSIS grant, CNCSIS Code 487/2005
INDIPHASO, E-LEARNING SYSTEM FOR THE DESIGN OF EMBEDDED HARDWARE-SOFTWARE APPLICATIONS, Project supported under CNCSIS grant No. 33371/29.06.2004 Theme 26, CNCSIS Code 516
PSICOME - Designing the command system for electrical machines by using FGPA and CPLD circuits. Project supported under CNCSIS grant, Theme 12, CNCSIS Code 223
Teaching Activity:
Teaching Assistant at Automatic Control and Applied Informatics Department - Introduction to Prolog Language (2005-2006)
Research activities:
Initiere in istoria si filosofia stiintei si tehnicii, Academia Romana, Bucuresti, Romania, 14-25 martie, 2011
Doctoral Intensive Summer School, "Al.I. Cuza" University, Iasi, Romania, 12-16 june, 2006
Floorplanning, partitioning and routing optimization algorithms (min. spanning/steiner trees);
Synthesis Algorithms of Complex Digital Circuits;
Complex circuits design and optimization by using Evolutionary Algorithms;
Evolvable Hardware - Concepts and Applications.
included in Who's Who in the World (Anniversary Edition), since 2008
Foreign Languages:
English - good
French - good;
Jobs:
Release Engineer for Linux and VM development at Oracle, Bucharest, Romania, since 2019
Senior Consultant at Infineon, Bucharest, Romania, 2017-2019
Senior Software QA Engineer at Nobel, Bucharest, Romania, 2016-2017
Senior integration Engineer at Orange, Bucharest, Romania, 2015-2016
System software Engineer at Luxoft Professional, Bucharest, Romania, 2014-2015
QA Architect at Intel Corporation, Bucharest, Romania, 2013-2014
Software Engineer at Thales Systems, Bucharest, Romania, 2009-2013
Digital design Engineer at "AsicAhead International", Bucharest, Romania, 2007-2008
System design Engineer at "FastPath Logic SRL", Iasi, Romania, 2006-2007
President of Youth FlyNET Organization, since 2004
System Engineer at PCNET, Broadband Internet Solutions,Iasi branch, Romania, part-time, 2004
ASIC Design Engineer at AsicArt L.T.D., Iasi, Romania, 1999-2001
System Administrator, SGI - Irix 5.x, Unix Environments, Autodesk SRL Iasi
Hobbies:
Psychology and Psycho-Analysis;
Music , Snooker , Table-Tennis and Basketball;
Last date when this page has been updated: 29 January 2021
Today's date: 09 May 2025